With emphasis on FPGA design integration, designed architecture and details for main processor boards (Wintegra 747, PowerQUICC MPC8260 uP,  TMS320C548 DSP, TMS320C6211 DSP and MC68360 uPs), Ethernet (hubs, switches, phys), time-slot interchangers, ADPCM transcoders, and voice to PCM. Included T1, E1 and DS3 framers, LIU’s, SLICs, SLACs, PCM, DACs, PLLs, ADPCM processors, clock adapters, clock multipliers, designed into FPGAs custom data rate converters and a custom 28 link TSI with 2048 cross-connectable channels including hardware signaling. Designed with Xilinx and Altera FPGAs and CPLDs (FPGAs: Cyclone I and II, Spartan IIe, XC5200 and XC4000 series, CPLD: XC9500), Verilog and VHDL.

FLEXmaster16 T1 Module: Responsibility for system and FPGA design integration, supports 16 T1 ports, 1 V.35 port, 6 10/100 Ethernet ports with integrated IP Router, 16 T1 mid-plane module-to-module cross-connect, 8 T1 ATM-IMA ports with IWF and CES capability, TDM Router software or ATM software, PWE capable with software download.

BROADway: Responsibility for design of PowerQUICC MPC8260 CPU cards. Modular multi-switch architecture. Base System supports up to 2 Ethernet, 60 T1/E1, 4 DS3/E3 and 4 OC3/STM1/EC1 interfaces. Stackable system expansion for higher port densities. Any to any DS0 and VT/TU granular digital cross connect switching. Integrated multi-port IP access routing. SONET/SDH add-drop multiplexing, Multi-layer, wireless carrier class reliability. Adaptive Switching:  node-level traffic protection. Integrated CSUs on all T1/E1 interfaces. Integrated Bit Error Rate Tester (BERT).

TRANSmaster: Responsibility for FPGA and DSP design integration, 2 to 1 ADPCM voice compression, supports up to 14.4 Kbps analog encoded data, 4 DS1/T1 or G.703 E1 interfaces, 4 integrated CSUs, 2 V.35/RS530 Data Ports, 2 integrated DSUs, Nx56/64 Kbps bypass, 10Mb Ethernet, digital cross-connect switch, D4-ESF conversion, performance monitoring of all network ports, drop and insert multiplexing, SNMP or VT100 managed, telnet supported, automatic protection switching (APS).

High speed optical character recognition and imaging     

Hardware designs include: 256 Gate Array character scoring circuit, real time adaptive threshold video filter, CCD camera control, real time video scaling, multi-access video memories, bus converters, print head positioner. Use of low and high density programmable logic and gate arrays. Developed and wrote system diagnostic and runtime code for 32010, 32030, 68010, and 68020 uPs.

High Speed Industrial Color Printer

Start-up. Specified and co-designed the image control for an eight print head bank (with scaling). Assisted with system definition and designed hardware to interface all I/O to Pentium PC including: image formatting and transfer, two-phase directional tachometer decode, stepper motor control, ink control, motion, heat, high voltage piezo fire pulse, thermocouple, pressure sensors, temperature sensors.

Two-dimensional bar code imaging & fingerprint verification

Start-up. Co-designed the first prototype circuit. Responsible for interface and development of custom CMOS imaging array, image DMA control, scan head servo control, CPU and companion I/O chip along with all I/O control logic, and LCD display control. Defined and evaluated imaging configuration requirements. Hitachi SH4 CPU, HD644651 companion, Xilinx 9500 CPLD, Epson display controller.

Gas blending equipment, ozone analyzers/generators

Designed the digital and analog architecture of a new generation of equipment. Experience with gas flow, pressure, temperature, regulation, reactions, adsorption, laminar/turbulent flow, ozone generation and measurement. Worked closely with California Air Resource Board. Environmental testing (designed a liquid nitrogen cooled test chamber). Wrote system code for 6800 uP. Transputer designs. Specified software functions.

Patented: #5,326,539 as inventor. Ozone generator.